Winbond 64Mb HyperRAM is designed with a function called as Chip ID Read (CIDR) function for
customer to identify the unique ID of each chip.
Further to the datasheet, this application note disclose the detail description of CIDR function for
customer easy to use the function for purpose requested by specific application.
CIDR function is able to be enabled as bleow sequence after power up.
The CIDR write sequence is set “configuration register 0 write” with OP code after power on.
The “configuration register 0 write” is consisted by CA47~CA0, while controlling the state of all address pins as
the OP code, data code is set as 8F0F after CA pin is set, Following is the CIDR enable sequence.
For the Chip ID read sequece, It must be executed by consecutive 3 chip ID code. Each chip ID code will
execute 3 command input with 8 bit test code, Register read is execute after consecutive 3 chip ID code set finish,
and chip ID will be readout at reset rising edge, while tCK must be bigger than 60ns, RESET=High > 30ns,
RESET=Low > 30ns. Following is the Chip ID read sequence.
Follow Chip ID read sequece, test mode is entry when each chip ID code is set. Each command input must
write test code into both ADD2 and ADD3. Following is the Chip ID read sequence.
Follow Chip ID read sequence, The “configuration register 0 (read)” must be set with OP code before chip ID
readout. The “configuration register 0 (read)” is consisted by CA47~CA0, while controlling the state of all
address pins as the OP code.
The chip ID read must be set 2 Latency count, Initial Latency count =5 clock ; Latency count1 + Latency
count2 =10 clock.
Test mode is exit after chip ID be readout, Following is the test mode exit code.
Following is the decode rule when chip ID be readout.
The valid chip ID code is CID to CID, when chip ID code be readout after CID, they are don’t care.
The CHIP ID is correctly readout under below conditions.